1. Field of the Invention
The invention relates in general to a storage capacitor structure for a memory cell in a semiconductor dynamic random access memory (DRAM) integrated circuit (IC) device and a process for fabricating the capacitor. In particular, the invention relates to a storage capacitor structure providing increased capacitance for a memory cell of DRAM IC devices, and its fabrication process.
2. Technical Background
As microprocessors become more and more powerful, the software programs they execute also become more and more complicated and require ever larger processing memory space. Since DRAMs currently provide the primary operating memory space for microprocessors, their operating characteristics are critical to the overall performance of the entire computer system. FIG. 1 is a schematic circuit diagram of a conventional memory cell unit that is organized in arrays to form the storage memory space for DRAM devices. FIG. 1 shows that the typical DRAM memory cell unit includes an n-type metal-oxide semiconductor field-effect transistor (NMOS transistor) 100 and a capacitor 102.
As shown in the drawing, the gate of the NMOS transistor 100 is connected to the word line WL of the device memory cell array, the source is connected to the bit line BL of the cell array, and the drain is connected to one electrode of the data storage capacitor 102, with the other electrode of the capacitor 102 being connected to the system ground plane. As persons skilled in the art are aware, a capacitor 102 utilized by the memory cell unit of FIG. 1 holds electric charges signifying the status of a stored data bit, while an NMOS transistor 100 is utilized as a bidirectional switch. Because the MOS transistor 100 has its source/drain pair functioning as either the current source or the drain, depending on whether the transistor is reading or writing digital data from or to the storage capacitor, respectively, the source and drain are generally designated as the source/drain pair herein.
A semiconductor structural configuration for a storage capacitor used in the memory cell units of a conventional DRAM device is schematically shown in the cross-sectional view of FIG. 2. The typical physical capacitor structure, which has a stacked configuration, is briefly examined with reference to this drawing. To fabricate such a capacitor element for the memory cell units of DRAM devices, a field oxide layer 202, a gate oxide layer 204, a first polysilicon layer 206, a sidewall spacer 208, and source/drain regions 210 of the NMOS transistor are sequentially formed over the surface of a silicon substrate 200. After the formation of the transistor, an oxide layer 212, such as silicon dioxide (SiO.sub.2), is then deposited over the substrate surface. Then, a contact opening 214 is formed at a designated location above the source/drain region 210 by etching the oxide layer 212. The contact opening 214 is then filled with a second polysilicon layer 216 to provide an external contact for the source/drain region 210 of the transistor element. Next, a dielectric layer 218 is deposited on top of the second polysilicon layer 216. The dielectric layer 218 can be, for example, a nitride/oxide (NO) layer or an oxide/nitride/oxide (ONO) layer. Finally, a third polysilicon layer 220 is formed atop the dielectric layer 218. Thus, at this stage, the second polysilicon layer 216, the dielectric layer 218, and the third polysilicon layer 220 form the storage capacitor 102 shown in the schematic circuit diagram of FIG. 1.
As is well known, capacitance and leakage characteristics of this storage capacitor are important to the performance of a DRAM device composed of memory cell arrays utilizing these capacitors. Specifically, a larger capacitor electrode surface area sustains data content longer, therefore requiring a lower memory cell content refresh rate. This results directly in improved memory subsystem performance in a host digital system. However, physically larger capacitors go against the trend of device miniaturization in manufacturing high-density DRAM devices.
Conventional storage capacitors for DRAM memory cell units such as the one depicted in FIG. 2 suffer from unsatisfactory capacitance characteristics. Specifically, conventional DRAM devices are equipped with storage capacitors for their memory cell units that have insufficient capacitance values. These capacitors require improvement to meet the standards set for modern microprocessor-based computer systems, in order to provide improved overall system performance.